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1st Korea HEP-FPGA Firmware Developers' Forum 2025

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강릉원주대학교 해양과학교육원

강릉원주대학교 해양과학교육원

강원 강릉시 사천면 해안로 1166
Jaebak Kim (Korea Uni), Jason Lee (University of Seoul), Minsuk Kim (KWNU)
Description

Introduction to the FPGA Firmware Developers' Forum for High-Energy Physics Students

The FPGA School is a four-day, fast-paced workshop designed to give graduate-level high-energy-physics (HEP) students a hands-on command of Field-Programmable Gate Arrays (FPGAs)—from fundamental concepts to cutting-edge AI acceleration.

The program blends concise lectures with extended laboratory sessions so participants can immediately apply what they learn.

Whether your goal is trigger-level data processing for experiments like CMS, ALICE, EIC etc., low-latency AI inference, or simply demystifying programmable logic, this school provides the practical foundation and expert guidance to accelerate your research journey.

Registration
registration
Register
  • Monday, 25 August
    • Day 1: Introduction to FPGAs
      • 15:00
        Registration and Check-in
      • 1
        Welcom to the 1st Korea HEP-FPGA Firmware Developers' Forum
      • 2
        Invited talk from AMD
      • 3
        FPGA project 2 - Yonsei
      • 16:50
        Coffee Break
      • 4
        FPGA project 3 - KNU
      • 5
        FPGA project 4 - UoS
      • 6
        Overview/plan of workshop and poll
      • 18:00
        Dinner
  • Tuesday, 26 August
    • Day 2: FPGA Algorithms
      • 7
        Introduction to FPGA
      • 09:45
        Coffee Break
      • 8
        Introduction to HDL
      • 10:45
        Coffee Break
      • 9
        Introduction to FPGA workflow and boards
      • 11:45
        Lunch
      • 10
        Introduction to simple FPGA resources (clock, sliceLUT)
      • 14:45
        Coffee Break
      • 11
        Hands on with FPGAs
      • 18:00
        Dinner
  • Wednesday, 27 August
    • Day 3: FPGA and AI
      • 12
        Writing firmware logic (Pipeline, and FSM)
      • 09:45
        Coffee Break
      • 13
        Introduction to simulation
      • 10:45
        Coffee Break
      • 14
        Introduction to AI
      • 11:45
        Lunch
      • 15
        Introduction to IP cores
      • 14:45
        Coffee Break
      • 16
        Hands on with FPGA and AI
      • 18:00
        Dinner
  • Thursday, 28 August
    • Day 4: FPGA Timing & High-Speed Communication
      • 17
        Introduction to HLS
      • 09:45
        Coffee Break
      • 18
        Introduction to ML4HLS
      • 10:45
        Coffee Break
      • 19
        Hands on with HLS and ML4HLS
      • 20
        Closing - Future Research Directions
      • 12:00
        Lunch and end of Forum
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