1st Korea HEP-FPGA Firmware Developers' Forum 2025

Asia/Seoul
강릉원주대학교 해양과학교육원

강릉원주대학교 해양과학교육원

강원 강릉시 사천면 해안로 1166
Jaebak Kim (Korea Uni), Jason Lee (University of Seoul), Minsuk Kim (KWNU)
Description

Introduction to the FPGA Firmware Developers' Forum for High-Energy Physics Students

The FPGA School is a four-day, fast-paced workshop designed to give graduate-level high-energy-physics (HEP) students a hands-on command of Field-Programmable Gate Arrays (FPGAs)—from fundamental concepts to cutting-edge AI acceleration.

The program blends concise lectures with extended laboratory sessions so participants can immediately apply what they learn.

Whether your goal is trigger-level data processing for experiments like CMS, ALICE, EIC etc., low-latency AI inference, or simply demystifying programmable logic, this school provides the practical foundation and expert guidance to accelerate your research journey.

Registration
registration
    • 14:00 20:20
      Day 1: Introduction to FPGAs
      • 15:00
        Registration and Check-in 1h
      • 16:00
        Welcom to the 1st Korea HEP-FPGA Firmware Developers' Forum 10m
      • 16:10
        Invited talk from AMD 20m
      • 16:30
        FPGA project 2 - Yonsei 20m
      • 16:50
        Coffee Break 10m
      • 17:00
        FPGA project 3 - KNU 20m
      • 17:20
        FPGA project 4 - UoS 20m
      • 17:40
        Overview/plan of workshop and poll 20m
      • 18:00
        Dinner 1h 20m
    • 09:00 20:00
      Day 2: FPGA Algorithms
      • 09:00
        Introduction to FPGA 45m
      • 09:45
        Coffee Break 15m
      • 10:00
        Introduction to HDL 45m
      • 10:45
        Coffee Break 15m
      • 11:00
        Introduction to FPGA workflow and boards 45m
      • 11:45
        Lunch 2h 15m
      • 14:00
        Introduction to simple FPGA resources (clock, sliceLUT) 45m
      • 14:45
        Coffee Break 15m
      • 15:00
        Hands on with FPGAs 3h
      • 18:00
        Dinner 1h
    • 09:00 20:00
      Day 3: FPGA and AI
      • 09:00
        Writing firmware logic (Pipeline, and FSM) 45m
      • 09:45
        Coffee Break 15m
      • 10:00
        Introduction to simulation 45m
      • 10:45
        Coffee Break 15m
      • 11:00
        Introduction to AI 45m
      • 11:45
        Lunch 2h 15m
      • 14:00
        Introduction to IP cores 45m
      • 14:45
        Coffee Break 15m
      • 15:00
        Hands on with FPGA and AI 3h
      • 18:00
        Dinner 1h
    • 09:00 14:35
      Day 4: FPGA Timing & High-Speed Communication
      • 09:00
        Introduction to HLS 45m
      • 09:45
        Coffee Break 15m
      • 10:00
        Introduction to ML4HLS 45m
      • 10:45
        Coffee Break 15m
      • 11:00
        Hands on with HLS and ML4HLS 45m
      • 11:45
        Closing - Future Research Directions 15m
      • 12:00
        Lunch and end of Forum 2h 20m